DocumentCode :
2606929
Title :
Bit-level allocation of multiple-precision specifications
Author :
Molina, M.C. ; Mendías, J.M. ; Hermida, R.
Author_Institution :
Dept. Arquitectura de Computadores y Automatica, Univ. Complutense de Madrid, Spain
fYear :
2002
fDate :
2002
Firstpage :
385
Lastpage :
392
Abstract :
This paper proposes an allocation algorithm able to perform the combined resource selection and operation binding of multiple-precision specifications that maximizes the bit-level reuse of hardware resources. Additionally, it presents an analytic method to estimate the amount of area that our approach could save in comparison with traditional allocation algorithms. In order to minimize the cost of the implementations obtained, the proposed algorithm produces circuits only influenced by the maximum number of bits calculated per cycle. This approach contrasts with the cost of implementations designed by traditional algorithms, which also depends on the number and widths of the operations executed in every cycle.
Keywords :
formal specification; processor scheduling; resource allocation; signal processing; DSP software; bit-level allocation; functional resources; high level synthesis; multiple-precision specifications; operation binding; resource selection; scheduling; storage resources; Algorithm design and analysis; Circuits; Computational efficiency; Costs; Delay; Design methodology; Hardware; High level synthesis; High performance computing; Resource management;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Digital System Design, 2002. Proceedings. Euromicro Symposium on
Print_ISBN :
0-7695-1790-0
Type :
conf
DOI :
10.1109/DSD.2002.1115396
Filename :
1115396
Link To Document :
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