Title :
VENICE: A Compact Vector Processor for FPGA Applications
Author :
Severance, Aaron ; Lemieux, Guy
Author_Institution :
Dept. of ECE, UBC, Vancouver, BC, Canada
fDate :
April 29 2012-May 1 2012
Abstract :
VENICE is a new soft vector processor (SVP) for FPGA applications that is designed for maximum through-put with a small number (1 to 4) of ALUs. By increasing clock speed and eliminating bottlenecks in ALU utilization, VENICE achieves over 2x better performance-per-logic block than VEGAS, the previous best SVP. VENICE is also simpler to program, as its instructions use standard C pointers into a scratchpad memory rather than vector registers.
Keywords :
field programmable gate arrays; vector processor systems; ALU utilization; FPGA applications; SVP; VENICE; compact vector processor; field programmable gate arrays; maximum throughput; performance-per-logic block; scratchpad memory; soft vector processor; standard C pointers; vector registers; Field programmable gate arrays; Parallel processing; Program processors; Programming; Registers; Vector processors; Vectors; FPGA; SIMD; scratchpad memory; soft processors; vector;
Conference_Titel :
Field-Programmable Custom Computing Machines (FCCM), 2012 IEEE 20th Annual International Symposium on
Conference_Location :
Toronto, ON
Print_ISBN :
978-1-4673-1605-7
DOI :
10.1109/FCCM.2012.55
