The Evaluation of CMOS Static-Charge Protection Networks and Failure Mechanisms Associated with Overstress Conditions as Related to Device Life

This study was performed to evaluate the input protection networks commonly used on CMOS product to protect the sensitive high impedance MOS-gate dielectric from damage or degradation resulting from transients associated with electrostatic discharge during handling. A human-model Thevenin equivalent circuit was developed and used to evaluate the effects of various stress levels and the effectiveness of the protection networks, and to determine the mechanism of failure. Accelerated life tests were conducted on a number of devices to determine if gate-oxide failures were latent defects.