An integrated CMOS image-rejection mixer system for low-jitter secondary frequency references

In complex mixed-signal system ICs there is usually the need for several clock frequencies, sometimes not frequency or phase related. The technique of simple phase-locked loop (PLL) designs places constraints on reference signal tracking and jitter performance. A subsystem designed to give a low-jitter high frequency reference clock from a low frequency PLL, without modifying loop dynamics or multiplying the frequency variations, is described. A CMOS integrated image rejection mixer system is presented using I and Q channel modulators and filters operating in the current domain. Rejection of the unwanted products is better than 35 dB and, from a 1.5 MHz signal with 20 ns p-p jitter, the output has less than 3 ns p-p at 15 MHz