Offset-compensated area-efficient switched-capacitor sum-gain amplifier

Two area-efficient switched capacitor sum-gain amplifiers (SGAs) are proposed. A parasitics-insensitive area-efficient sum-gain amplifier is presented, which reduces the capacitance spread ratio approximately to max_i(√|A_sga,i|), where A_sga,i is the gain factor of the input channel i and |A_sga,i| ⩾ 1 in high-gain applications. This reduction in capacitance spread ratio translates to a corresponding reduction in silicon area usage. As an improvement of the circuit, a second SGA design is presented. It employs an offset storage capacitor to reduce the output offset voltage, while preserving the reduced capacitance spread ratio of the first design. The output offset voltage of this improved SGA is reduced by a factor more than max_i(√|A_sga,i|). The advantages of such designs are demonstrated through simulation results with SWITCAP-II and measured responses from discrete IC components