High resolution multi-frequency digital phase locked loop

A fully digital phase locked loop (PLL) for synchronizing a generated clock to an external clock is presented. It can be used as a clock synchronizer in an application that is constructed of several components which use an associated bus and must operate synchronously. The PLL is digital in terms of phase-detection, phase shift by a tapped delay-line, and phase-error correction using a digital machine. When switching to another frequency, smooth switching is performed without losing synchronization. The PLL has zero jitter under any working conditions. No RESET signal is needed in order for the PLL to operate in a chip that requires the PLL to be synchronized at the end of RESET