Test sequence generation for realistic faults in CMOS ICs based on standard cell library

We present in this paper a new concept of test sequence generation for realistic faults in CMOS ICs based on the pre-determined testing conditions of cells in the standard cell library. In a one-time effort, fabrication level defects in each cell in the standard cell library are extensively analyzed via circuit simulations. Optimal test sequence of each cell is then determined and pre-stored for later use. For a given circuit under test (CUT), the automatic test sequence generation (ATSG) program generates the test sequence of the circuit under test by trying to satisfy all test sequences of all cells in the given netlist. The results on ISCAS85 benchmark circuits show that the proposed approach reduces test generation time and test size significantly while providing the capability to adapt to virtually any fault/defect model