Test sequence generation for realistic faults in CMOS ICs based on standard cell library

Author

Song, Peilin ; Lo, Jien-Chung

Author_Institution

Dept. of Electr. & Comput. Eng., Rhode Island Univ., Kingston, RI, USA

fYear

1996

fDate

6-8 Nov 1996

Firstpage

114

Lastpage

122

Abstract

We present in this paper a new concept of test sequence generation for realistic faults in CMOS ICs based on the pre-determined testing conditions of cells in the standard cell library. In a one-time effort, fabrication level defects in each cell in the standard cell library are extensively analyzed via circuit simulations. Optimal test sequence of each cell is then determined and pre-stored for later use. For a given circuit under test (CUT), the automatic test sequence generation (ATSG) program generates the test sequence of the circuit under test by trying to satisfy all test sequences of all cells in the given netlist. The results on ISCAS85 benchmark circuits show that the proposed approach reduces test generation time and test size significantly while providing the capability to adapt to virtually any fault/defect model

Keywords

CMOS digital integrated circuits; CMOS logic circuits; automatic test software; circuit analysis computing; integrated circuit testing; logic testing; CMOS ICs; automatic test sequence generation program; circuit simulations; fabrication level defects; realistic faults; standard cell library; test sequence generation; Automatic testing; Benchmark testing; Circuit analysis; Circuit faults; Circuit simulation; Circuit testing; Fabrication; Libraries; Production; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI Systems, 1996. Proceedings., 1996 IEEE International Symposium on

Conference_Location

Boston, MA

ISSN

1550-5774

Print_ISBN

0-8186-7545-4

Type

conf

DOI

10.1109/DFTVS.1996.572009

Filename

572009