Title :
The 65nm tunneling field effect transistor (TFET) 0.68μm2 6T memory cell and multi-Vth device
Author :
Nirschl, Th ; Henzler, St. ; Fischer, J. ; Bargagli-Stoffi, A. ; Fulde, M. ; Sterkel, M. ; Teichmann, P. ; Schaper, U. ; Einfeld, J. ; Linnenbank, C. ; Sedlmeir, J. ; Weber, C. ; Heinrich, R. ; Ostermayr, M. ; Olbrich, A. ; Dobler, B. ; Ruderer, E. ; Kako
Author_Institution :
Inst. for Tech. Electron., Munich Tech. Univ., Germany
Abstract :
The tunneling field effect transistor (TFET) is fabricated using a 65nm standard CMOS process flow. The short-narrow TFET offers an on-current of 550μA/μm which is comparable to the reference MOSFET device. Due to the integrated substrate/well contact the effective area of the TFET is smaller compared to the corresponding MOSFET. Thus, the size of a system-on-a-chip design is reduced by more than 5%. The quantum-mechanical TFET is able to extend the epoch of the CMOS technology by showing reduced short channel effects and smaller leakage currents. A multi-threshold TFET device is proposed which does not need additional implantation steps. A 0.68μm2 6 transistor memory cell is fabricated using TFETs and MOSFETs showing the compatibility of MOSFET and TFET and a decrease of the memory array area of approximately 3%.
Keywords :
CMOS memory circuits; MOSFET; leakage currents; system-on-chip; tunnelling; 6 transistor memory cell; 65 nm; CMOS process; MOSFET device; integrated substrate; leakage currents; multi-threshold TFET device; quantum-mechanical TFET device; short channel effect reduction; short-narrow TFET device; system-on-a-chip design; tunneling field effect transistor; well contact; CMOS process; CMOS technology; Diodes; Doping; FETs; Leakage current; Logic arrays; MOSFET circuits; System-on-a-chip; Tunneling;
Conference_Titel :
Solid-State Device Research Conference, 2005. ESSDERC 2005. Proceedings of 35th European
Print_ISBN :
0-7803-9203-5
DOI :
10.1109/ESSDER.2005.1546613
