DocumentCode
2607674
Title
Electrical Testing for Design Verification and Operating Margins
Author
Foss, R.C.
Author_Institution
MOSAID INC., Box 11123 St. H, Ottawa K2H 7T8. (613)-820-7316
fYear
1978
fDate
28581
Firstpage
75
Lastpage
75
Abstract
The MOS dynamic RAM presents an extreme example of the problems inherent in testing complex integrated functions. Establishing that a dynamic RAM design is operating as its designer intended under all permitted operating conditions, is a monumentally difficult task. Historically, subtle problems have only come to light when large scale use of a particular part is already established. It is then of little consolation that a supposedly new problem is often found to be closely related to one in an earlier generation of part.
Keywords
Circuit testing; Coupling circuits; DRAM chips; Decoding; Large-scale systems; National electric code; Variable structure systems;
fLanguage
English
Publisher
ieee
Conference_Titel
Reliability Physics Symposium, 1978. 16th Annual
Conference_Location
San Diego, CA, USA
ISSN
0735-0791
Type
conf
DOI
10.1109/IRPS.1978.362822
Filename
4208212
Link To Document