Title :
Compensation of 2nd harmonic distortion in a 4-FET linearised transconductor circuit
Author :
Parker, A.E. ; Haigh, D.G.
Author_Institution :
Dept. of Electron., Macquarie Univ., Sydney, NSW, Australia
Abstract :
A method of compensation for the second harmonic distortion of a 4-FET linearized transconductor circuit is proposed and evaluated. The sensitivity of the second harmonic distortion level to the compensation parameters is evaluated. Taking account of integrated circuit process parameters, it is concluded that compensation is possible for wide bandwidths up to a decade in frequency. As a first step in understanding the mechanism causing distortion in the circuit, an expression and set of curves showing the effect of signal mismatch in a FET-pair are presented
Keywords :
MESFET integrated circuits; analogue processing circuits; compensation; field effect analogue integrated circuits; harmonic distortion; FET-pair; SHD; compensation parameters; integrated circuit process parameters; linearised transconductor circuit; second harmonic distortion; signal mismatch; Circuit synthesis; Equations; FETs; Frequency; Gallium arsenide; Harmonic distortion; MESFETs; Signal synthesis; Transconductors; Voltage;
Conference_Titel :
Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on
Conference_Location :
Chicago, IL
Print_ISBN :
0-7803-1281-3
DOI :
10.1109/ISCAS.1993.393924
