TGICAPP: an asynchronous distributed approach to test vector generation based on circuit partitioning on parallel processors

The authors present an asynchronous distributed approach to test vector generation for digital electronics, based on circuit partitioning that is executable on parallel processors for combinational digital designs. This approach utilizes maximal parallelism inherent in the circuit under test. Test generation is complete when consistent logical values have been assigned at each of the primary inputs of the design or an unresolved conflict is observed implying that the fault in question is untestable. The algorithm models the total test generation process through entities; one entity representing each component of the circuit under test, and two additional special entities. An entity representing a component receives messages from other entities and determines whether it has arrived at an unsolvable scenario or that justification and/or sensitization requests ought to be propagated to other models. The special entities model the primary inputs and outputs and determine whether a consistent solution has been obtained or an unsolvable scenario has been reached. Performance measures based on example circuits are discussed