Title :
Test strategies for fine pitch wafer level packaged devices
Author :
Jayabalan, Jayasanker ; Rotaru, Mihai D. ; Chun, Deng ; Hua, Feng Han ; Iyer, Mahadevan K. ; Ooi, B.L. ; Leong, M.S. ; Ang, Simon ; Tay, Andrew A O ; Keezer, David ; Rao, Tummala
Author_Institution :
Nano/Microsystems Integration Lab., Nat. Univ. of Singapore, Singapore
Abstract :
The objective of this work is to be able to test wafer level packaged devices at 5 GHz given tight mechanical constraints such as very fine pitch (of the order of 100 micron) and large pin count of thousands. Good electrical contact at the wafer level after the attachment of interconnects is needed for producing reliable electrical test results.. This paper describes the details of modeling, fabrication and the test methodology as applied to the electrical characterization of fine pitch and large pin count wafer level packaged devices.
Keywords :
chip scale packaging; fine-pitch technology; integrated circuit interconnections; integrated circuit testing; soldering; 5 GHz; interconnects attachment; interposer fabrication; large pin count; tight mechanical constraints; very fine pitch; wafer level packaged devices; Automatic testing; Circuit testing; Contacts; Electronic equipment testing; Frequency; Hardware; Integrated circuit interconnections; Packaging; Probes; Wafer scale integration;
Conference_Titel :
Electronics Packaging Technology, 2003 5th Conference (EPTC 2003)
Print_ISBN :
0-7803-8205-6
DOI :
10.1109/EPTC.2003.1271553
