A MEMS based interposer for nano-wafer level packaging test

We have developed a novel MEMS based interposer which severs as the electromechanical interface between the device chip under test (DUT), and the test processor. It is capable of fanning out of 100 μm pitch I/Os to 750 μm pitch pads which is compatible with conventional PCB technology. The interposer has both power and ground planes near the signal traces to enable the high frequency transmission. It was fabricated on a silicon substrate using semiconductor and micro-machining processes. Through wafer vias were formed by KOH anisotropic etching. Conductive materials were filled in the vias to form interconnection. The interposer also has compliant structures which give vertical compliance to the probe pads. Because silicon substrate is used, there is no thermal mismatch, which gives our interposer the potential of being used in wafer level burn-in test.