Influence of Electrical Bias Level on 85/85 Test Results of Plastic Encapsulated 4K RAMs

Samples of plastic encapsulated NMOS/LSI dynamic 4K RAMs were placed on 85°C/85% R.H. tests at four (4) different bias levels. No level exceeded specification maximums. Tests were continued as long as practical to allow observation of the entire failure distribution of most of the test groups. Over 394,000 actual device hours were accumulated. Detailed failure analysis was performed on all failures to allow for proper censoring of life test data. Censored failure mechanisms included mobile ionic contamination, package lead corrosion and plating, electrical overstress (mishandling), tester error, and in several cases, electroplating of gold from the ball bonds. Failure data representing only failures due to moisture related electrochemical corrosion of the IC aluminum metallization were analyzed. This failure mechanism accounted for 78% of the failures. Failure distributions of each test group were of lognormal nature. Three test groups were studied (Chip A/ Package 1, Chip B/Package 1 and Chip B/Package 2). Test results indicated an exponential acceleration of the failure rate with increase in electrical bias level. Bias -vs. median life curves for the three test groups examined as a composite allow for statements as to the moisture resistance characteristics of the packages and of the IC chips.