Development of a novel filled no-flow underfill material for flip chip applications

Flip chip package design has a significant drawback related to the mismatch of coefficient of thermal expansion (CTE) between the silicon die and the organic substrate. This CTE mismatch creates stress on the solder joints during thermal excursions, which reduces the fatigue lifetime of the solder joints. This leads to premature failures of the package. However, package reliability can be improved by the application of an underfill material. In this communication, we report the development of a novel filled no-flow underfill material utilizing proprietary filler technology, which provides a previously unobtainable balance of low CTE, high glass transition temperature (Tg), and good solder joint formation. The fluxing parameters and effect of catalyst level on assembly yield are presented. Assembly results (yield, void area) are presented and compared with commercially available no-flow underfill materials.