Title :
A CMOS square-law programmable floating resistor
Author :
Sakurai, Satoshi ; Ismail, Mohammed
Author_Institution :
Ohio State Univ., Columbus, OH, USA
Abstract :
A CMOS architecture for a floating linear resistor which exploits the square-law model of the MOS transistor is presented. The architecture is programmable by a DC control voltage, and it is fabricated in a 2-μm p-well CMOS MOSIS process. The resistor occupies 210 μm × 270 μm, consumes .4-4 mW with ±5 V supply and exhibits a signal-to-noise-ratio (at1% total harmonic distortion) of more than 100 dB over a 1-V range of the DC control voltage
Keywords :
MOSFET; harmonic distortion; resistors; 0.4 to 4 mW; 2 micron; CMOS; DC control voltage; linear resistor; p-well MOSIS process; signal-to-noise-ratio; square-law programmable floating resistor; total harmonic distortion; CMOS process; Circuits; MOSFETs; Resistors; Semiconductor device modeling; Threshold voltage; Variable structure systems; Very large scale integration; Virtual colonoscopy; Voltage control;
Conference_Titel :
Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on
Conference_Location :
Chicago, IL
Print_ISBN :
0-7803-1281-3
DOI :
10.1109/ISCAS.1993.393939
