Title :
A concurrent two-step flash analogue-to-digital converter architecture
Author :
Vital, João C. ; Franca, José E.
Author_Institution :
Electr. & Comput. Eng. Dept., Inst. Superior Tecnico, Lisbon, Portugal
Abstract :
An alternative recycling two-step flash analog-digital converter architecture is presented where the concurrent operation of two multiplying digital-analog converters (MDACs) with a single flash quantizer yields an improved throughput rate over the traditional architecture. The effects of subpath mismatches in the overall converter performance are estimated. A design example is given to demonstrate its feasibility
Keywords :
CMOS integrated circuits; analogue-digital conversion; A/D convertor architecture; concurrent operation; flash quantizer; multiplying digital-analog converters; recycling type; subpath mismatches; throughput rate; two-step flash ADC; Analog integrated circuits; Capacitors; Computer architecture; Delay; Feedback loop; Phased arrays; Recycling; Sampling methods; Throughput; Voltage;
Conference_Titel :
Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on
Conference_Location :
Chicago, IL
Print_ISBN :
0-7803-1281-3
DOI :
10.1109/ISCAS.1993.393942
