On the scalability of source/drain current enhancement in thin film sSOI

Author

Augendre, E. ; Eneman, G. ; De Keersgieter, A. ; Simons, V. ; De Wolf, I. ; Ramos, J. ; Brus, S. ; Pawlak, B. ; Seven, S. ; Leys, F. ; Sleeckx, E. ; Locorotondo, S. ; Ercken, M. ; de Marneffe, J.-F. ; Fei, L. ; Seacrist, M. ; Kellerman, B. ; Goodwin, M. ;

Author_Institution

Interuniv. Microelectron. Center, IMEC, Leuven, Belgium

fYear

2005

fDate

12-16 Sept. 2005

Firstpage

301

Lastpage

304

Abstract

This paper demonstrates for the first time the scalability of source/drain current enhancement on low-doped thin film strained silicon on insulator (sSOI) substrate. Current improvement is maintained in narrow channel NFETs despite the relaxation from biaxial to uniaxial tensile strain after mesa patterning. Using strained contact etch-stop layers (sCESL), additional boost is achieved in short devices, resulting in 50% improvement in the drive current of 50 nm gate length devices with respect to conventional reference SOI process.

Keywords

field effect transistors; semiconductor thin films; silicon-on-insulator; stress effects; thin film transistors; 50 nm; NFET device; biaxial tensile strain; drive current improvement; mesa patterning; source-drain current enhancement; strained contact etch-stop layers; strained silicon on insulator; thin film sSOI substrate; uniaxial tensile strain; Capacitive sensors; Dielectric thin films; Scalability; Semiconductor thin films; Strain measurement; Substrates; Tensile strain; Thin film devices; Transistors; Uniaxial strain;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Device Research Conference, 2005. ESSDERC 2005. Proceedings of 35th European

Print_ISBN

0-7803-9203-5

Type

conf

DOI

10.1109/ESSDER.2005.1546645

Filename

1546645