Low temperature sintering process for deposition of nano-structured metal for nano IC packaging

Author

Kwan, Wong Wai ; Kripesh, Vaidyanathan ; Iyer, Mahadevan K. ; Gupta, Manoj ; Tay, Andrew A O ; Tummala, Rao

Author_Institution

Inst. of Microelectron., Singapore, Singapore

fYear

2003

fDate

10-12 Dec. 2003

Firstpage

551

Lastpage

556

Abstract

This paper presents the study of some nano-sized metal powders, and the processes of depositing these on silicon wafers, for use in nano-structured wafer level interconnects. Nano-powders, ∼50-100 nm, of copper and silver, obtained by electro-explosion of the metal wire, are used in this study. Pastes were obtained by suspension of the nano metallic powder in surfactants, organic carriers and reducing agents. The pastes were printed onto surface-treated silicon wafers and sintered at around 400°C. Results show that there is a potential of lowering the sintering temperature to 200°C, which would be more ideal for microelectronics applications.

Keywords

copper; elemental semiconductors; integrated circuit interconnections; integrated circuit metallisation; integrated circuit packaging; nanoelectronics; nanoparticles; powders; silicon; silver; sintering; suspensions; 200 degC; 400 degC; 50 to 100 nm; Ag-Si; Cu-Si; low temperature sintering process; metal wire electro-explosion; nano IC packaging; nano-sized metal powders; nano-structured metal deposition; nano-structured wafer level interconnects; organic carriers; paste printing; paste suspensions; reducing agents; silicon wafers; sintering temperature; surfactants; Copper; Fatigue; Integrated circuit packaging; Microelectronics; Powders; Semiconductor materials; Silicon; Silver; Temperature; Wafer scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics Packaging Technology, 2003 5th Conference (EPTC 2003)

Print_ISBN

0-7803-8205-6

Type

conf

DOI

10.1109/EPTC.2003.1271582

Filename

1271582