Characterization of negative resistance and bipolar latchup in thin film SOI transistors by two-dimensional numerical simulation

Summary form only given. Two-dimensional numerical simulation is used to characterize the breakdown and negative resistance behavior of thin-film transistors. The negative resistance is modeled as a thermal effect. A thermal resistance coefficient is used in conjunction with the output power to modify the temperature-dependence carrier mobility in an addition iterative loop. The value of thermal resistance input to the program is somewhat speculative, but is based on experimental estimates of temperature rise, in both FIPOS and SIMOX devices, as a function of output power. Good quantitative agreement is achieved using values of thermal coefficient in the range 5-10°C per mW per micron. The low breakdown voltage in the subthreshold region is shown to be due to lowering of the potential barrier at the source junction. As a guide, simulation predicts that when the barrier is lowered by approximately 0.8 V, the transistor no longer functions under the control of the gate, and a lateral bipolar effect governs the current flow from source to drain. The reduction in the source potential barrier is also responsible for the onset of a latchup effect in thin-film devices