Title :
Mechanical failure strength characterization of silicon dice
Author :
Chong, Desmond Y R ; Lee, W.E. ; Pang, John H.L. ; Low, T.H. ; Lim, B.K.
Author_Institution :
Adv. Package & Design Center, United Test & Assembly Center Ltd., Singapore, Singapore
Abstract :
Modem Integrated Circuit technology has driven the trend in die size and thickness decrease of the microelectronics circuits. High stresses induced in the die due to packaging, assembly and reliability tests begin to surface. Due to its brittle nature, moderate stresses could result in detrimental fracture in the die. However failure strength (stress) of the silicon die has not been readily available, and it is difficult to determine fracture strength of a silicon wafer because of its large diameter and thin layer which could break easily. Hence it would be meaningful for silicon strength to be characterized at die level. This paper discusses an approach for the characterization of silicon die failure strength, using a simple three-point bending method commonly used for brittle material testing. This helps to provide a better understanding of the stress accumulated in the die before failure. The effects of die thickness, die size and backgrinding patterns on the die stress have been investigated. The results revealed that die stress at failure actually increases with thinner die, indicating that a thinner die in a package can withstand higher load before failure. As anticipated, die with a thicker width can subject to greater stress before breakage, as higher load is needed to induce crack propagating through a larger grain boundary. Macroscopic analysis on the cracked die samples also revealed cleavage fracture and chevron patterns related to brittle fracture surfaces. It could be seen that threshold value for die strength is largely dependent on die size and die thickness. The threshold failure stress values would be useful for solving future die failure problems encountered in new packaging and process development work.
Keywords :
bending strength; brittle fracture; elemental semiconductors; fracture toughness; fracture toughness testing; integrated circuit packaging; silicon; IC packages; Si; brittle fracture; brittle material testing; chevron patterns; cleavage fracture; cracked samples; die size decrease; die thickness decrease; failure strength; macroscopic analysis; moderate stresses; silicon die failure; three-point bending method; Assembly; Circuit testing; Integrated circuit packaging; Integrated circuit reliability; Integrated circuit technology; Microelectronics; Modems; Silicon; Stress; Surface cracks;
Conference_Titel :
Electronics Packaging Technology, 2003 5th Conference (EPTC 2003)
Print_ISBN :
0-7803-8205-6
DOI :
10.1109/EPTC.2003.1271591