The prediction of circuit performance variations for deep submicron CMOS processes

Author

Gneiting, Thomas ; Jalowiecki, Ian

Author_Institution

Fachhochschule Esslingen-Hochschule fur Tech., Germany

fYear

1996

fDate

6-8 Nov 1996

Firstpage

140

Lastpage

148

Abstract

In this paper, a method is described which can be used to predict the variation of circuit performance, e.g. the maximum clock rate, due to fluctuations of the semiconductor manufacturing process, A huge amount of measurements on CMOS test devices of two process generations (0.8 and 0.5 micron) has been performed to develop a description of the statistical variations. Based on this data and the use of a physical simulation model for the MOS devices, a prediction of the circuit performance of two future CMOS process generations (0.35 and 0.25 micron) has been undertaken. At least, the results of this study will be applied to a special type of circuits, to predict the feasibility of synchronous clock and data distribution on future ULSI devices

Keywords

CMOS integrated circuits; ULSI; integrated circuit manufacture; integrated circuit modelling; statistical analysis; 0.25 to 0.8 micron; ULSI devices; circuit performance variation prediction; deep submicron CMOS processes; maximum clock rate; physical simulation model; semiconductor manufacturing process fluctuations; statistical variations; synchronous clock distribution; synchronous data distribution; CMOS process; Circuit optimization; Circuit simulation; Circuit testing; Clocks; Fluctuations; Manufacturing processes; Performance evaluation; Predictive models; Semiconductor device testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI Systems, 1996. Proceedings., 1996 IEEE International Symposium on

Conference_Location

Boston, MA

ISSN

1550-5774

Print_ISBN

0-8186-7545-4

Type

conf

DOI

10.1109/DFTVS.1996.572015

Filename

572015