• DocumentCode
    2608967
  • Title

    Failure Analysis Techniques and Failure Mechanisms Utilizing a Plasma Etcher

  • Author

    Gajda, J.J. ; DeLorenzo, D.J. ; Wade, J.A.

  • Author_Institution
    International Business Machines Corporation, Data Systems Division, Hopewell Junction, New York 12533. (914) 897-6939
  • fYear
    1979
  • fDate
    28946
  • Firstpage
    171
  • Lastpage
    177
  • Abstract
    The utilization of plasma etching for selective layer removal of semiconductor device passivation films, polysilicon or substrate silicon, is playing a more and more significant role in delineation of specific failure mechanisms or process introduced anomalies. The advantages of selective removal of materials without destroying the failure site or its morphology are discussed, as well as complementary techniques used in performance of the various analyses. Analysis results are given involving bipolar and FET structures that identify 1. Sites of metal alloy penetration causing excessive leakage currents in bipolar logic circuitry. 2. Opens in test site double level metal interconnection vias due to current stress. 3. Corrosion sites on interconnection metallurgy. 4. FET gate oxide quality after polysilicon gate electrode removal. 5 Test site C-4 terminal interconnection via opens.
  • Keywords
    Circuit testing; Etching; FETs; Failure analysis; Integrated circuit interconnections; Passivation; Plasma applications; Plasma devices; Plasma materials processing; Semiconductor devices;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Reliability Physics Symposium, 1979. 17th Annual
  • Conference_Location
    San Diego, CA, USA
  • ISSN
    0735-0791
  • Type

    conf

  • DOI
    10.1109/IRPS.1979.362889
  • Filename
    4208282