Scalability of strained nitride capping layers for future CMOS generations

Author

Eneman, G. ; Jurczak, M. ; Verheyen, P. ; Hoffmann, T. ; De Keersgieter, A. ; De Meyer, K.

Author_Institution

IMEC, Heverlee, Belgium

fYear

2005

fDate

12-16 Sept. 2005

Firstpage

449

Lastpage

452

Abstract

This paper investigates the layout dependence of strain induced in transistor channels, for technologies that use strained nitride capping layers (or contact etch stop layers - CESL). It is shown that the sensitivity in dense structures will be reduced for thinner nitride capping layers and scaled spacers. In isolated structures, the effects of STI- and CESL-induced stress are additive. Guidelines for CESL-scaling in future technologies are proposed.

Keywords

CMOS integrated circuits; etching; isolation technology; CMOS; contact etch stop layers; strained nitride capping layers; transistor channels; Capacitive sensors; Compressive stress; Electronic switching systems; Etching; Guidelines; Isolation technology; MOSFETs; Scalability; Space technology; Tensile stress;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Device Research Conference, 2005. ESSDERC 2005. Proceedings of 35th European

Print_ISBN

0-7803-9203-5

Type

conf

DOI

10.1109/ESSDER.2005.1546681

Filename

1546681

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2609100