Enhancing the PCI bus to support real-time streams

Author

Scottis, Marios G. ; Krunz, Marwan ; Liu, Max M -K

Author_Institution

Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA

fYear

1999

fDate

10-12 Feb 1999

Firstpage

303

Lastpage

309

Abstract

In this paper we present an access scheduling scheme for real-time streams (RTS) over the peripheral component interconnect (PCI) bus. We derive a bus model based on the rate monotonic scheduling (RMS) algorithm that guarantees the timing quality of service (QoS) for real-time streams over the PCI bus. The proposed model is valid for constant-bit-rate (CBR) as well as for variable-bit-rate (VBR) streams. We define the effective bus utilization (EBU) as the worst case bus utilization and we determine the value of the internal latency timer (ILT) that minimizes EBU. Finally, we present some simulation results to demonstrate the practicality of the proposed scheme

Keywords

peripheral interfaces; quality of service; real-time systems; PCI bus; access scheduling; constant-bit-rate; internal latency timer; peripheral component interconnect; rate monotonic scheduling; real-time streams; timing quality of service; variable-bit-rate; Computer architecture; Computer graphics; Delay; Electronics industry; Processor scheduling; Quality of service; Real time systems; Streaming media; Throughput; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Performance, Computing and Communications Conference, 1999 IEEE International

Conference_Location

Scottsdale, AZ

ISSN

1097-2641

Print_ISBN

0-7803-5258-0

Type

conf

DOI

10.1109/PCCC.1999.749453

Filename

749453