Thermal failure simulation for electrical overstress in semiconductor devices

Author

Díaz, Carlos ; Duvvury, Charvaka ; Kang, Sung-Mo

Author_Institution

Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA

fYear

1993

fDate

3-6 May 1993

Firstpage

1389

Abstract

Electrical overstress (EOS) and electrostatic discharge (ESD) constitute one of the most dominant threats to integrated circuits (ICs). A nonlinear 2-D/1-D thermal simulator suitable for ESD/EOS thermal failure modeling in ICs is reported. The unboundedness of the thermal problem is addressed by a special set of boundary conditions, making the thermal simulation task computationally efficient. Simulated power-to-failure vs. time-to-failure relationships (power profiles) for various combinations of major IC structural parameters are presented and compared with experimental data

Keywords

circuit analysis computing; digital simulation; electrostatic discharge; failure analysis; integrated circuit modelling; integrated circuit reliability; integrated circuit testing; IC structural parameters; boundary conditions; electrical overstress; electrostatic discharge; nonlinear 2D/1D thermal simulator; power profiles; power-to-failure; semiconductor devices; thermal failure modeling; time-to-failure; Circuit simulation; Computational modeling; Earth Observing System; Electrostatic discharge; Instruments; Integrated circuit modeling; Process design; Protection; Semiconductor devices; Thermal conductivity;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on

Conference_Location

Chicago, IL

Print_ISBN

0-7803-1281-3

Type

conf

DOI

10.1109/ISCAS.1993.393991

Filename

393991