STI-induced damage and hot-carrier reliability in the narrow width short channel NMOSFET fabricated using global strained-Si technology

The width dependence of threshold voltage (V_t) in the strained-Si NMOSFET relative to that of the control bulk Si device is examined. The contrasting behavior of V_t, for decreasing channel width (W_drawn) at a given channel length (L_drawn), could be ascribed to the increased concentration of the channel dopant at the regions near the STI (shallow trench isolation)/gate edge of the strained device. Dopant enhancement is attributed to the abundance of interstitial defect sites located in both the strained-Si and the SiGe layer, due to the lattice strain arising from the STI process. Hot-carrier degradation is found to be marginally higher in the narrow-width strained device.