DocumentCode
260957
Title
Multicore speedup models using frequency scaling with fixed power budget
Author
Seungwon Lee ; Seung Hun Kim ; Won Woo Ro
Author_Institution
Sch. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea
fYear
2014
fDate
15-18 Jan. 2014
Firstpage
1
Lastpage
2
Abstract
Utilization of a core with delay faults by frequency scaling reduces performance degradation in a multicore processor. When the frequency of a delay fault core is decreased, frequencies of the rest cores can be increased within a fixed power budget since the amount of dynamic power is proportional to the clock frequency. We propose two speedup models based on modified Amdahl´s law for the frequency scaling of a multicore architecture. From the models, we derive an attainable maximum speedup of a multicore processor with a delay fault core.
Keywords
multiprocessing systems; clock frequency; fixed power budget; frequency scaling; modified Amdahl´s law; multicore processor; multicore speedup models; Boosting; Clocks; Degradation; Delays; Mathematical model; Multicore processing; DVFS; Speedup model; delay fault;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Information and Communications (ICEIC), 2014 International Conference on
Conference_Location
Kota Kinabalu
Type
conf
DOI
10.1109/ELINFOCOM.2014.6914403
Filename
6914403
Link To Document