Maximum likelihood estimation for yield analysis [IC manufacture]

This paper presents an iterative maximum likelihood (ML) estimation method for statistical analysis of yield loss. By means of Inductive Fault Analysis (IFA) and circuit simulation, the mapping between defect types to the corresponding fault signature is constructed. Using the count of each fault signature occurrence, which is provided by a tester, the most likely causes of low yield are identified automatically without the need for physically deprocessing the defective ICs. We show that our method is superior to current practices for yield analysis which use a least squares fit or partial tester data to estimate defect densities