An in-sequence guaranteed space-memory-memory Clos-network architecture

Out-of-sequence (OOS) is a problem faced by most multistage Clos-network switches. One classical three-stage Clos-network switch structure is to use round-robin to achieve load balancing at the first stage, then switch stage by stage at the latter two stages, using SAR (segments and reassemble) which has to deal with OOS. To address this problem, we propose Frame-based Fair Round-robin (FFRR) for the first stage. Theoretical analyses and simulation results show that FFRR achieves excellent performance - 100% throughput and low delay. Then we develop a three-stage Clos-network structure, which performs outstandingly without speedup.