Fast mixed-mode simulation for accurate MOS bridging fault detection

Author

Chuang, Weitong ; Hajj, Ibrahim N.

Author_Institution

Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA

fYear

1993

fDate

3-6 May 1993

Firstpage

1503

Abstract

A dynamic mixed-mode approach for the simulation of physical faults in MOS VLSI circuits is described, with emphasis on bridging faults. Bridging faults in digital circuits could cause the affected gates or subcircuits, and possibly their immediate fanouts, to behave as analog subcircuits in a localized region within a design. Mixed digital gate-level and switch-level simulation with dynamic localized analog simulation, depending on the location of a fault, provides a robust and fast way to perform digital fault simulation accurately and fast enough for practical fault simulation

Keywords

MOS logic circuits; VLSI; circuit analysis computing; digital simulation; fault diagnosis; integrated circuit modelling; logic testing; MOS VLSI; MOS bridging fault; analog subcircuits; digital fault simulation; gate-level simulation; localized region; mixed-mode simulation; physical faults; switch-level simulation; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Digital circuits; Electrical fault detection; Fault detection; Logic testing; Switching circuits; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on

Conference_Location

Chicago, IL

Print_ISBN

0-7803-1281-3

Type

conf

DOI

10.1109/ISCAS.1993.394020

Filename

394020