DocumentCode
2609751
Title
Efficient test vectors for ISCAS sequential benchmark circuits
Author
Lee, Soo Y. ; Saluja, Lewal K.
Author_Institution
Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
fYear
1993
fDate
3-6 May 1993
Firstpage
1511
Abstract
The sequential automatic test pattern generation system FASTEST is implemented with new heuristics to produce efficient test vectors for sequential circuits. The efficiency of FASTEST in terms of the quality of test vectors is demonstrated. The test vectors provide excellent fault coverage by fairly short test sequences. The profile of the ISCAS benchmark circuits is also described
Keywords
automatic testing; binary sequences; fault diagnosis; integrated circuit testing; logic testing; sequential circuits; FASTEST; ISCAS sequential benchmark circuits; automatic test pattern generation system; fault coverage; heuristics; short test sequences; test vectors; Automatic test pattern generation; Automatic testing; Benchmark testing; Circuit faults; Circuit testing; Iterative algorithms; Logic circuits; Sequential analysis; Sequential circuits; System testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on
Conference_Location
Chicago, IL
Print_ISBN
0-7803-1281-3
Type
conf
DOI
10.1109/ISCAS.1993.394022
Filename
394022
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