DocumentCode
2609817
Title
An examination of feedback bridging faults in digital CMOS circuits
Author
Koch, Bernd K. ; Müller-Glaser, Klaus D.
Author_Institution
Inst. of Comput. Aided Circuit Design, Univ. of Erlangen-Nurnberg, Erlangen-Tennenlohe, Germany
fYear
1993
fDate
3-6 May 1993
Firstpage
1527
Abstract
A new model for feedback bridging faults at the transistor level is presented. The model particularly considers the external connections of the feedback loop. Criteria for the occurrence of oscillations and storage effects are calculated, and the parameters relevant for their occurrence are given. The similarity between oscillation and storage is shown. The results are evaluated using HSPICE (simulation program with IC emphasis) and a standard cell library
Keywords
CMOS logic circuits; SPICE; circuit analysis computing; circuit feedback; circuit oscillations; integrated circuit modelling; logic CAD; HSPICE; digital CMOS circuits; external connections; feedback bridging faults; oscillations; standard cell library; storage effects; transistor level; CMOS digital integrated circuits; Circuit faults; Circuit simulation; Circuit synthesis; Electric resistance; Feedback circuits; Inverters; Libraries; Semiconductor device modeling; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on
Conference_Location
Chicago, IL
Print_ISBN
0-7803-1281-3
Type
conf
DOI
10.1109/ISCAS.1993.394026
Filename
394026
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