Title :
Bounds for distributed parameter trees
Author :
Marinov, Corneliu A. ; Neittaanmäki, Pekka
Abstract :
The interconnection wires in VLSI circuits are modelled by telegraph equations. Upper and lower bounds are given for node voltages of a tree network composed of such wires and ended in lumped capacitors. These bounds are easily computable from circuit parameters and are sufficiently tight to be used in initial design stages of digital circuits
Keywords :
VLSI; distributed parameter networks; integrated circuit design; integrated circuit interconnections; network parameters; network topology; trees (mathematics); VLSI circuits; circuit parameters; distributed parameter trees; initial design stages; interconnection wires; lower bounds; lumped capacitors; node voltages; telegraph equations; tree network; upper bounds; Capacitors; Delay; Differential equations; Integrated circuit interconnections; Mathematical model; Mathematics; Telegraphy; Very large scale integration; Voltage; Wires;
Conference_Titel :
Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on
Conference_Location :
Chicago, IL
Print_ISBN :
0-7803-1281-3
DOI :
10.1109/ISCAS.1993.394032
