Title :
An expandable chip design for gray-scale morphological operations
Author :
Sheu, Ming-hwa ; Wang, Jhing-Fa ; Lee, Jau-Yien ; Liu, An-Ying
Author_Institution :
Dept. of Electr. Eng., Nat. Cheng-kung Univ., Tainan, Taiwan
Abstract :
A new pipeline architecture to perform 3 × 3 gray-scale morphological operations in real time is presented. This architecture has both lower hardware cost and faster operation time than other presented architectures. Under 1.2-mm CMOS technique, this architecture is implemented as one chip with 0.5 × 0.6 cm2 area size. The chip can be used as a basic building block to construct a chip size for any larger size morphological operations
Keywords :
CMOS digital integrated circuits; feature extraction; image processing equipment; parallel architectures; pipeline processing; 1.2 micron; chip size; expandable chip design; gray-scale morphological operations; hardware cost; operation time; pipeline architecture; Application software; Chip scale packaging; Costs; Gray-scale; Hardware; Morphological operations; Morphology; Pipelines; Probes; Throughput;
Conference_Titel :
Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on
Conference_Location :
Chicago, IL
Print_ISBN :
0-7803-1281-3
DOI :
10.1109/ISCAS.1993.394035
