A 1.5V 10-bit 5 MS/s CMOS algorithmic ADC

A 1.5V 10-bit 5 MS/s low power algorithmic analog-to-digital converter (ADC) based on double-sampling technique is proposed. At the front-end, a timing-skew-insensitive double-sampled Miller-capacitance-based sample-and-hold circuit (S/H) is employed to enhance the dynamic performance of the algorithmic ADC. Double sampling technique is also applied to multiplying digital-to-analog converter (MDAC). This scheme provides a better power efficiency for the proposed algorithmic ADC. Furthermore, bootstrapped switch achieves rail-to-rail signal swing at low-voltage power supply. This ADC design achieves DNL and INL of 0.36LSB and 0.45LSB respectively, while SNDR is 59.6dB and SFDR is 70.5dB at an input frequency of 400kHz. Operating at 5MS/s sampling rate under a single 1.5V power supply, the power consumption is 5.6mW in TSMC 0.35μm CMOS 2P4M process.