A unified approach for off-line and on-line testing of VLSI systems

Author

Lala, P.K. ; Yang, S. ; Busaba, F.

Author_Institution

Dept. of Electr. Eng., North Carolina A&T State Univ., Greensboro, NC, USA

fYear

1996

fDate

6-8 Nov 1996

Firstpage

195

Lastpage

203

Abstract

BIST (Built-in self-test) techniques are often used to improve the testability of VLSI systems. Self-checking techniques are used to detect the presence of a fault in a system during normal operation. BIST techniques can be used only in on-line mode, whereas self-checking enables on-line resting. This paper presents a new approach for combining BIST and self-checking, which utilizes the resources of both to enhance the testability of VLSI systems

Keywords

VLSI; built-in self test; integrated circuit testing; BIST; VLSI system; built-in self-test; fault detection; off-line testing; on-line testing; self-checking; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Electrical fault detection; Fault detection; Feeds; Monitoring; System testing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI Systems, 1996. Proceedings., 1996 IEEE International Symposium on

Conference_Location

Boston, MA

ISSN

1550-5774

Print_ISBN

0-8186-7545-4

Type

conf

DOI

10.1109/DFTVS.1996.572025

Filename

572025

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2610089