DocumentCode
2610105
Title
A high throughput-rate architecture for 8*8 2D DCT
Author
Sheu, Ming-hwa ; Lee, Jau-Yien ; Wang, Jhing-Fa ; Suen, An-Nan ; Liu, Liang-Ying
Author_Institution
Dept. of Electr. Eng., Nat. Cheng-Kung Univ., Tainan, Taiwan
fYear
1993
fDate
3-6 May 1993
Firstpage
1587
Abstract
A new architecture for VLSI implementation of an 8 × 8 2D discrete cosine transform (DCT) is proposed. The main merits of this architecture are: (1) the multipliers are replaced by memory look-up tables; (2) no input registers are required to save a column of input data; (3) the chip performance is independent of data width; and (4) the latency (the largest delay path) is short
Keywords
VLSI; digital signal processing chips; discrete cosine transforms; parallel architectures; pipeline processing; table lookup; 2D discrete cosine transform; VLSI implementation; chip performance; data width; high throughput-rate architecture; input data; latency; memory look-up tables; Data compression; Delay; Discrete cosine transforms; Equations; High performance computing; Pipelines; Read-write memory; Registers; Table lookup; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on
Conference_Location
Chicago, IL
Print_ISBN
0-7803-1281-3
Type
conf
DOI
10.1109/ISCAS.1993.394041
Filename
394041
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