DocumentCode
2610162
Title
Fault-tolerant shuffle-exchange and de Bruijn networks capable of quick broadcasting
Author
Tsuda, Nobuo
Author_Institution
NTT Commun. & Inf. Systems Labs., Musashino, Japan
fYear
1996
fDate
6-8 Nov 1996
Firstpage
231
Lastpage
239
Abstract
The construction of fault-tolerant processor arrays with shuffle-exchange or base-2 de Bruijn networks using an advanced spare-connection scheme for k-out-of-n redundancies called “generalized additional bypass linking” is described. The connection scheme uses bypass links with wired OR connections to spare processing elements (PEs) without external switches, and can reconfigure complete arrays by tolerating faulty portions in these PEs and links. The wired OR connections help to limit the number of connections to the spare PEs, and these connections are made so that the primary PEs are at an inter-PE distance of 3 or more away from each other and me connected to the same bypass link in parallel. The designs of spare-connections were formulated as a node coloring problem of a graph with a minimum distance of 3, and the chromatic numbers that correspond to the number of connections of spare PEs were evaluated by using a newly-devised coloring algorithm. The proposed scheme can be used for constructing various k-out-of-n configurations capable of quick broadcasting by using spare circuits, and is superior to conventional schemes in terms of extra PE connections and reconfiguration control
Keywords
fault tolerant computing; graph colouring; graph theory; hypercube networks; redundancy; chromatic number; de Bruijn network; fault tolerance; generalized additional bypass linking; graph; k-out-of-n redundancy; node coloring algorithm; processor array; quick broadcasting; reconfiguration control; shuffle-exchange network; spare connection; wired OR connection; Algorithm design and analysis; Broadcasting; Circuit faults; Fault tolerance; Hypercubes; Joining processes; Laboratories; Redundancy; Switches; Tree graphs;
fLanguage
English
Publisher
ieee
Conference_Titel
Defect and Fault Tolerance in VLSI Systems, 1996. Proceedings., 1996 IEEE International Symposium on
Conference_Location
Boston, MA
ISSN
1550-5774
Print_ISBN
0-8186-7545-4
Type
conf
DOI
10.1109/DFTVS.1996.572029
Filename
572029
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