Easily testable PLA-based FSMS

Author

Avedillo, M.J. ; Quintana, J.M. ; Huertas, J.L.

Author_Institution

Centro Nacional de Microelectron., Sevilla, Spain

fYear

1993

fDate

3-6 May 1993

Firstpage

1603

Abstract

A new hardware scheme for easily testable programmable logic array (PLA)-based finite state machines is proposed. With the authors´ scheme, all combinationally irredundant crosspoint faults in the PLA logic implementation are testable. Test generation is easily accomplished because short systematic initialization sequences exist for each internal state in the machine and unit length distinguishing sequences. The scheme is outlined. It consists of the addition of some state transitions and their outputs to the state transition graph (STG) of the machine. A test generation procedure which does not require fault simulation or the manipulation of the STG of the machine is described

Keywords

asynchronous circuits; automatic testing; binary sequences; fault diagnosis; finite state machines; logic arrays; logic testing; combinationally irredundant crosspoint faults; finite state machines; internal state; programmable logic array; state transition graph; state transitions; systematic initialization sequences; test generation procedure; unit length distinguishing sequences; Automata; Controllability; Hardware; Large Hadron Collider; Logic arrays; Logic testing; Programmable logic arrays; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on

Conference_Location

Chicago, IL

Print_ISBN

0-7803-1281-3

Type

conf

DOI

10.1109/ISCAS.1993.394045

Filename

394045