Title :
On fault modeling and fault tolerance of antifuse based FPGAs
Author_Institution :
Texas Instruments, Inc., Dallas, TX, USA
Abstract :
The fault modeling, fault location, and fault tolerance of antifuse-based field programmable gate arrays (FPGAs) are discussed. The antifuse faults are divided into two categories, i.e., those that can be detected before programmation, and those that can be detected only after programmation. It is shown that some of the antifuse open and short faults may also appear as delay faults. The redundancy inherent in the FPGAs is utilized fully to achieve fault tolerance without extra circuitry
Keywords :
delays; fault diagnosis; field programmable gate arrays; logic testing; programmable logic arrays; redundancy; antifuse based FPGAs; delay faults; fault location; fault modeling; fault tolerance; programmation; redundancy; Circuit faults; Fault tolerance; Field programmable gate arrays; Logic arrays; Logic programming; Logic testing; Programmable logic arrays; Redundancy; Routing; Semiconductor process modeling;
Conference_Titel :
Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on
Conference_Location :
Chicago, IL
Print_ISBN :
0-7803-1281-3
DOI :
10.1109/ISCAS.1993.394050
