Title :
A MOdular and Reprogrammable Real-time Processing Hardware, MORRPH
Author :
Drayer, Thomas H. ; King, William E., IV ; Tront, Joseph G. ; Conners, Richard W.
Author_Institution :
Bradley Dept. of Electr. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
Abstract :
The MORRPH architecture is a general purpose reconfigurable processing unit, primarily designed to solve real time 2D image processing problems. Its robust architecture allows it to be used for other applications including 1D signal processing, 2D cellular automata problems, and 3D image processing. The modular, open ended architecture consists of an M×N rectangular mesh of processing elements (PEs), called the processing array. Each PE contains a single field programmable gate array (FPGA) chip and interconnections for several support chips. The FPGA chips within the PEs provide an array of logic resources, consisting of combinational logic functions, flip flops and internal chip routing resources. The types of support chips which are included in the PEs are not fixed, they are determined by the requirements of the computational task performed by the MORRPH. These memory, arithmetic, or processing support chips are specified and assembled on the MORRPH board for each particular application that is developed. Currently, the MORRPH architecture is implemented as an adapter card for the Industry Standard Architecture (ISA) computer bus. A constructed prototype with a 23 array of PEs is used in a current machine vision system to perform low level image processing functions. A significant performance increase is obtained by using the MORRPH as a preprocessing unit for the host processing computer. The MORRPH architecture is shown to be an inexpensive solution for relatively simple or very complex real time processing tasks
Keywords :
field programmable gate arrays; flip-flops; image processing; microprocessor chips; real-time systems; reconfigurable architectures; 1D signal processing; 2D cellular automata problems; 3D image processing; FPGA chips; ISA computer bus; Industry Standard Architecture; MORRPH architecture; MOdular and Reprogrammable Real-time Processing Hardware; adapter card; combinational logic functions; field programmable gate array chip; flip flops; general purpose reconfigurable processing unit; internal chip routing resources; logic resources; machine vision system; modular and reprogrammable real time processing hardware; open ended architecture; processing array; processing elements; real time 2D image processing problems; rectangular mesh; Array signal processing; Computer architecture; Field programmable gate arrays; Hardware; Image processing; Logic arrays; Logic functions; Process design; Programmable logic arrays; Robustness;
Conference_Titel :
FPGAs for Custom Computing Machines, 1995. Proceedings. IEEE Symposium on
Conference_Location :
Napa Valley, CA
Print_ISBN :
0-8186-7548-9
DOI :
10.1109/FPGA.1995.477404