Trojan Immune Circuits Using Duality

The problem of hardware Trojan detection has been recently studied extensively. The use of traditional testing strategies to detect hardware Trojans is not effective because the probability of triggering a hardware Trojan during testing is very low. Moreover, the small size of the Trojan compared to the overall size of the chip reduces the impact of the Trojan on side channels such as static and dynamic power. Process variations in modern technologies will even distort this impact and reduce the efficiency of such methods to detect the Trojan. In this work, we propose the development of new Trojan immune circuits where Trojans are easier to detect using traditional testing methods. The main idea is that each circuit has a designed dual. By testing the dual, one can easily detect a Trojan embedded in the original circuit. On the other hand, if an attacker tries to hide the Trojan in the dual, the Trojan will be detectable in the original circuit. We study an example dual design using gates with dual function. We also present attacks and countermeasures on the dual to provide guidelines for the low level implementation of the proposed architecture. Experimental results show that a Trojan hidden in a circuit can be detected by applying a few random test inputs on the dual. In addition, the estimated average area overhead to construct the example dual is 5.5%.