DocumentCode :
2610395
Title :
FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration
Author :
Pnevmatikatos, D. ; Becker, T. ; Brokalakis, A. ; Bruneel, K. ; Gaydadjiev, G. ; Luk, W. ; Papadimitriou, K. ; Papaefstathiou, I. ; Pell, O. ; Pilato, C. ; Robart, M. ; Santambrogio, M.D. ; Sciuto, D. ; Stroobandt, D. ; Todman, T.
Author_Institution :
Found. for Res. & Technol.-Hellas, Heraklion, Greece
fYear :
2012
fDate :
5-8 Sept. 2012
Firstpage :
234
Lastpage :
241
Abstract :
The FASTER project aims to ease the definition, implementation and use of dynamically changing hardware systems. Our motivation stems from the promise reconfigurable systems hold for achieving better performance and extending product functionality and lifetime via the addition of new features that work at hardware speed. This is a clear advantage over the more straightforward software component adaptivity. However, designing a changing hardware system is both challenging and time consuming. The FASTER project will facilitate the use of reconfigurable technology by providing a complete methodology that enables designers to easily specify, analyse, implement and verify applications on platforms with general-purpose processors and acceleration modules implemented in the latest reconfigurable technology. To better adapt to different application requirements, the tool-chain will support both region-based and micro-reconfiguration and provide a flexible run-time system that will efficiently manage the reconfigurable resources. We will use applications from the embedded, high performance computing, and desktop domains to demonstrate the potential benefits of the FASTER tools on metrics such as performance, power consumption and total ownership cost.
Keywords :
embedded systems; energy conservation; parallel processing; performance evaluation; reconfigurable architectures; FASTER project; FASTER tools; acceleration modules; desktop domains; dynamically changing hardware system; embedded computing; facilitating analysis and synthesis technologies for effective reconfiguration; flexible run-time system; general-purpose processors; hardware speed; high-performance computing; microreconfiguration; performance metrics; power consumption; product functionality; product lifetime; reconfigurable resource management; region-based reconfiguration; tool chain; Computer architecture; Field programmable gate arrays; Hardware; Power demand; Schedules; Software; XML; partial reconfiguration; reconfigurable computing; relocation; run-time reconfiguration; run-time system; tools for reconfiguration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Digital System Design (DSD), 2012 15th Euromicro Conference on
Conference_Location :
Izmir
Print_ISBN :
978-1-4673-2498-4
Type :
conf
DOI :
10.1109/DSD.2012.59
Filename :
6386896
Link To Document :
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