A performance-driven approach to the high-level synthesis of DSP algorithms

In high-level synthesis, it is necessary to find the design with the highest suitability to the design directives under various quality criteria. Optimization techniques result in quality increases impossible to achieve in other steps of the synthesis process. Two optimization techniques are presented, one to raise the throughput and another to reduce the area and output latency of the design. A scheduling method which can obtain rate-optimal schedules with high processor utilization is also presented. These techniques form an approach for the high-level synthesis of digital signal processing algorithms for high performance designs