Title :
RTL synthesis for systolic arrays
Author :
Robertson, W. ; Periyalwar, S. ; Phillips, W.J.
Author_Institution :
Tech. Univ. of Nova Scotia, Halifax, NS, Canada
Abstract :
A register-transfer-level systolic synthesis strategy for multidimensional systolic arrays is described. Optimum utilization of silicon is attained by rescheduling operations on functional units across processing elements. The synthesis tool examines the tradeoff between sharing of functional units, additional buses, and the size of the controller
Keywords :
high level synthesis; scheduling; systolic arrays; RTL synthesis; additional buses; functional units; multidimensional systolic arrays; processing elements; register-transfer-level systolic synthesis; rescheduling operations; systolic arrays; Application software; Computer networks; Control system synthesis; Design optimization; Digital signal processing; Network synthesis; Resource management; Silicon; Space technology; Systolic arrays;
Conference_Titel :
Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on
Conference_Location :
Chicago, IL
Print_ISBN :
0-7803-1281-3
DOI :
10.1109/ISCAS.1993.394062
