Algorithm-Architecture Co-Optimization of Area-Efficient SDR Baseband for Highly Diversified Digital TV Standards

The rapidly evolving and diversifying wireless landscape demands highly flexible wireless chipsets. Due to the ultimate programmability, SDR solutions are becoming more and more attractive. However, the programmability overhead is still a concern for the silicon area cost of SDR solutions. In this work, we prove that, with algorithm and architecture co- design, SDR solutions can be very competitive even when compared to highly optimized ASICs. Specifically, we show a baseband processor design that can support ISDB-T, DVB-T and ATSC, but the area cost is still comparable to the combination of ASICs which handle the three terrestrial digital TV standards respectively.