Signal transition graph constraints for speed-independent circuit synthesis

The synthesis of asynchronous circuits is difficult in VLSI design. Transition based specification such as signal transition graphs (STGs) are simple and powerful in specifying and synthesizing asynchronous behavior. A relationship is established between the signal transition graph syntactic constraints, i.e., persistency and complete state coding (CSC). A direct proof is presented which shows that a persistency violation either does not affect hazards or, if it does, there results a complete state coding violation. The authors´ results give the conditions under which a persistency violation may lead to a complete state coding violation