Title :
ECCSyn-A synthesis tool for ECC circuits
Author :
Su, Chauchin ; Wang, Jyrghong
Author_Institution :
Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan
Abstract :
EECSyn is an automated tool dedicated for the synthesis of error control coding (ECC) circuits. EECSyn takes H matrices as inputs and produces physical layouts automatically. A greedy algorithm and an exhaustive search algorithm are implemented for ECC logic minimization. They achieve 37.7% and 40.8% reduction in gate counts respectively
Keywords :
circuit layout CAD; error correction codes; logic CAD; minimisation of switching nets; ECC circuits; ECCSyn; H matrices; error control coding; exhaustive search algorithm; gate counts; greedy algorithm; logic minimization; physical layouts; synthesis tool; Automatic control; Circuit synthesis; Circuit testing; Decoding; Equations; Error correction; Error correction codes; HDTV; Minimization methods; Synthesizers;
Conference_Titel :
Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on
Conference_Location :
Chicago, IL
Print_ISBN :
0-7803-1281-3
DOI :
10.1109/ISCAS.1993.394071
