Fault characterization and testability analysis of emitter coupled logic and comparison with CMOS & BiCMOS circuits

Author

Esonu, M.O. ; Al-Khalili, D. ; Rozon, C.

Author_Institution

Dept. of Electr. & Comput. Eng., R. Mil. Coll. of Canada, Kingston, Ont., Canada

fYear

1993

fDate

3-6 May 1993

Firstpage

1714

Abstract

The effects of physical defects on emitter-coupled logic (ECL) OR/NOR, AND and reference voltage circuits are investigated. The faults induced by the defects are analyzed and classified into two groups, i.e., logical faults and performance degradation faults such as delay, current and voltage transfer characteristic (VTC) or noise margin (NM) faults. These results are compared with those of an equivalent set of BiCMOS and CMOS gates. It is shown that logical together with VTC fault testing will detect about 98% of the faults in the ECL gates. For equivalent BiCMOS and CMOS gates, logical with delay fault testing provides the highest fault coverage

Keywords

NOR circuits; bipolar logic circuits; delays; emitter-coupled logic; fault diagnosis; integrated circuit noise; logic testing; reference circuits; AND circuits; OR/NOR circuits; VTC fault testing; delay fault testing; emitter coupled logic; fault coverage; logical faults; logical testing; noise margin; performance degradation faults; physical defects; reference voltage circuits; testability analysis; voltage transfer characteristic; BiCMOS integrated circuits; Circuit faults; Circuit testing; Coupling circuits; Degradation; Delay; Logic circuits; Logic testing; Performance analysis; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on

Conference_Location

Chicago, IL

Print_ISBN

0-7803-1281-3

Type

conf

DOI

10.1109/ISCAS.1993.394073

Filename

394073